High speed logic circuits such as but not limited to latches or flip-flops are required to respond to input signals very quickly. An input signal is provided to such a logic circuit via a fast transfer gate that ideally allows the input signal to propagate towards the logic circuit only during a transparent mode while preventing the input signal to reach the logic circuit during a non-transparent mode.
Typically, multiple transfer gates receive signals that were not intended to be provided to them (via parasitic capacitors also referred to as coupling capacitors) and such signals can affect signals on transfer gate input.
This unwanted influence can cause an input signal to propagate through the transfer gate even if the transfer gate is in a non-transparent mode. These unwanted influence can, for example cause voltage drops below zero volts or even below negative values that their absolute values equal the power supply level. This unwanted influence can cause a voltage peak that exceeds the level of the power supply. Such voltage drops or rise can open transfer gates that are supposed to be in a non-transfer mode.
FIG. 1 illustrates a prior art circuit 10 that includes three nodes N1 21, N2 22 and N3 23 that are connected to each other by parasitic capacitor C12 11 and C23 12. Data signal D1 80 is provided via first node N1 21 to first transfer gate 30. Nodes N2 22 and N3 23 are connected to a transfer gate and a latch which are not shown for convenience of explanation.
First transfer gate 30 includes first NMOS transistor 32 and first PMOS transistor 34. The source of PMOS transistor 34 and the drain of transistor 32 are connected to each other, the gate of first NMOS transistor 32 receives clock signal CLK 70 while the gate of first PMOS transistor 34 receives inverted clock signal CLK_INV 72. Inverted clock signal 72 is provided by clock signal inverter 56 that receives as input clock signal CLK 70.
The output of first transfer gate 30 is connected to input node 62 of first inverter 52. Input node 62 of first inverter 52 is connected to an output of second transfer gate 46. The input node of second transfer gate 40 is connected to an output of second inverter 54. The input of second inverter 54 is connected to the output of first inverter 52 and to output node 64 of latch 50.
Second transfer gate 46 includes second PMOS transistor 42 and second NMOS transistor 44. The source and drains of transistors 42 and 44 are connected to each other, the gate of second PMOS transistor 42 receives clock signal CLK 70 while the gate of second NMOS transistor 44 receives inverted clock signal CLK_INV 70.
Ideally, when clock signal CLK 70 is high first transfer gate 30 is in a non-transparent mode. When clock signal CLK70 input data signal 80 is not expected to change. Nevertheless, if the voltage at second node N2 22 or third nodes N3 33 changes (for example from “0” to “1” or from “1” to “0”) these changes can cause temporary changes in the voltage at first node 21 can cause one of the transfer gate transistor to conduct and to cause changes in the data stored in latch 50. These temporary changes may change the state of latch 50.
When transfer gate 30 is in a non-transfer mode the gate NMOS transistor 32 receives zero volts. If the voltage at first node N2 22 (Vsource) is equal −Vtn (wherein Vtn is the threshold voltage of NMOS transistor 32) then the voltage drop between the source and gate of NMOS transistor 32 is equal to Vtn (Vgs=Vgate−Vsource=0−(−Vtn)=Vtn) and the NMOS transistor 32 conducts. If the voltage at node N2 22 is below −Vtn then the Vgs exceeds Vtn and NMOS transistor 32 conducts.
When transfer gate 30 is in a non-transfer mode the gate PMOS transistor 34 receives a high level voltage that is referred to as Vdd. If the voltage at first node N2 22 (Vsource) equals Vdd+Vtp (wherein Vtp is the threshold voltage of PMOS transistor 34) then the voltage drop between the source and gate of PMOS transistor 34 equals Vtp (Vgs=Vsource−Vgate=(Vdd+Vdd)−Vdd=Vtp) and the PMOS transistor 34 conducts. If the voltage at node N2 22 exceeds (Vdd+Vtp) then Vgs exceeds Vtp and PMOS transistor 34 conducts.
In some cases the transfer gate is preceded by a logical gate. Placing a logical gate near the transfer gate reduces the coupling capacitance but slows the circuit. An exemplary circuit that includes such as logic gate is illustrated in FIG. 2.
FIG. 2 illustrates a prior art circuit 11 that includes OR logic gate 90, first transfer gate 30, clock signal inverter 56, second transfer gate 46, first inverter 50, second inverter 54, and AND logic gate 94.
OR logic gate 90 performs an OR operation between a scan enable signal SE 91 and a clock control signal EN 99 that has to pass through a fast critical path.
AND logic gate 94 performs an AND operation between clock signal CLK 70 and the data signal at the input of first inverter 50. The output of AND logic gate 94 is the output signal of circuit 11. Circuit 11 is adapted to receive a clock signal and to provide a gated clock signal 95 to another circuit. Circuit 11 as well as circuit 10 is susceptible to errors caused by noise.
There is a need to provide an efficient method and device for reducing noise induced errors.